1. Field of the Invention
The present invention relates to a CMOS image sensor, and a method for manufacturing the same, that improves the light-receiving efficiency of a photodiode.
2. Discussion of the Related Art
An image sensor is a semiconductor device that converts an optical image to an electric signal. Image sensors can be broadly categorized into charge coupled devices (CCD) and complementary metal oxide semiconductor (CMOS) image sensors.
In a CCD, respective metal-oxide-silicon MOS capacitors are positioned adjacently, wherein electric charge carriers are stored in and transferred to the capacitors. However, a CMOS image sensor adopts CMOS technology, which uses a control circuit and a signal processing circuit as the peripheral circuit. The CMOS image sensor uses a switching method of sequentially detecting output signals by forming a predetermined number of MOS transistors to correspond to the number of pixels.
A CMOS image sensor has advantages of low power consumption, low production cost and high integration. CMOS image sensors have received a great amount of attention as substitutes for CCDs because of the development of this recent technology.
A CMOS image sensor may be classified into 3T-type, 4T-type, or 5T-type, according to a number of transistors in the CMOS image sensor. The 3T-type CMOS image sensor is comprised of one photodiode and three transistors, and the 4T-type CMOS image sensor is comprised of one photodiode and four transistors.
An equivalent circuit and a layout for the 3T-type CMOS image sensor according to the related art will be described as follows.
FIG. 1 is an equivalent circuit diagram of a 3T-type CMOS image sensor according to the related art. FIG. 2 is a layout of one pixel in the 3T-type CMOS image sensor according to the related art. FIG. 3 is a cross sectional view along I-I′ of FIG. 2.
As shown in FIG. 1, a unit pixel of the 3T-type CMOS image sensor according to the related art comprises one photodiode PD and three NMOS transistors T1, T2 and T3. A cathode of the photodiode PD is connected with a drain of the first NMOS transistor T1 and a gate of the second nMOS transistor T2.
Also, sources of the first and second nMOS transistors T1 and T2 are connected with a power supplying line for receiving a reference voltage RDD. A gate of the first nMOS transistor T1 is connected with a reset line for receiving a reset signal RST.
A source of the third nMOS transistor T3 is connected with a drain of the second nMOS transistor, and a drain of the third NMOS transistor T3 is connected with a read circuit through a signal line. Further, a gate of the third nMOS transistor T3 is connected with a word line for receiving a selection signal SLCT.
The first nMOS transistor T1 functions as a reset transistor Rx. Also, the second nMOS transistor T2 is a drive transistor Dx, and the third nMOS transistor T3 is a select transistor Sx.
In the unit pixel of the 3T-type CMOS image sensor, as shown in FIGS. 2 and 3, an active area 10 and a field area are defined in a p-type semiconductor substrate 1. Then, one photodiode 20 is formed in a large sized portion of the active area 10. Also, respective gate electrodes 120, 130 and 140 of three transistors are overlapped with the remaining portion of the active area 10.
N-type impurity ions may be more deeply implanted into the photodiode 20 than the remaining portions of the active area.
The reset transistor Rx is formed by the gate electrode 120, the drive transistor Dx is formed by the gate electrode 130, and the select transistor Sx is formed by the gate electrode 140. Impurity ions may be implanted into the active area 10 of the respective transistors excluding portions below the gate electrodes 120, 130 and 140, thereby forming source and drain regions in the respective transistors.
Accordingly, a power voltage Vdd is applied to the source and drain regions between the reset transistor Rx and the drive transistor Dx. Also, the source and drain regions provided at one side of the select transistor Sx are connected with the read circuit.
Although not shown, the respective gate electrodes 120, 130 and 140 are connected with signal lines. Each one end of the signal lines has a pad being connected with an external driving circuit.
The three photodiodes constitute one pixel. That is, one pixel is made by forming red, green and blue color filter layers on the respective three photodiodes.
FIG. 4 is a cross sectional view of a CMOS image sensor according to the related art. As shown in FIG. 4, a related art CMOS image sensor is defined with a sensing unit and a peripheral driving unit. On a semiconductor substrate 11, a field oxide layer (not shown) is formed to define an active area, and then a plurality of photodiodes PD 12 and transistors 13 are formed in the semiconductor substrate 11 of the active area. Then, a first insulating interlayer 14 is formed on a surface of the semiconductor substrate 11 including the photodiodes 12 and transistors 13. The first insulating layer 14 may have a thickness of about 7450 Å.
Then, a plurality of metal lines M1, M2 and M3 for one unit pixel are formed on the first insulating interlayer 14, wherein the plurality of metal lines M1, M2 and M3 are positioned not to shield the incident light. Second to fourth insulating interlayers 15, 16 and 17 for insulation of the respective metal lines M1, M2 and M3 and a planarization layer 18 are formed. The first metal line M1 may be formed at a thickness of about 5070 Å on the first insulating interlayer 14. Then, the second insulating interlayer 15 is formed on the surface of the semiconductor substrate 11 including the first metal line M1. The second insulating layer 15 may be formed at a thickness of about 7300 Å.
Then, the second metal line M2 may be formed at a thickness of about 5070 Å on the second insulating interlayer 15, and the third insulating interlayer 16 may be formed at a thickness of about 7300 Å on the surface of the semiconductor substrate 11 including the second metal line M2. Also, the third metal line M3 may be formed at a thickness of about 9630 Å on the third insulating interlayer 16, and the fourth insulating interlayer 17 may be formed at a thickness of about 4000 Å on the surface of the semiconductor substrate 11 including the third metal line M3. Then, the planarization layer 18, which may have a thickness of about 3000 Å, is formed on the fourth insulating interlayer 17.
To realize a color image, an RGB color filter layer 19 is formed on the planarization layer 18 of the sensing unit, and a micro-lens 21 is formed on the RGB color filter layer 19. To form the micro-lens 21, after coating a photoresist, the photoresist is patterned to be left over the photodiode 12, and is reflowed by baking so as to obtain a desired curvature. The micro-lens 21 concentrates the incident light into the photodiode 12.
FIGS. 5A and 5B are cross sectional views of a CMOS image sensor fabricated by a method according to the related art.
As shown in FIG. 5A, a p-well is formed by implanting p-type impurity ions to a semiconductor substrate 1. After defining an active area and a field area in the semiconductor substrate 1, an STI (Shallow Trench Isolation) 2 is formed in the field area.
Then, a gate oxide layer 3 and a conductive layer are formed on a surface of the semiconductor substrate 1, and are then selectively removed to form gate electrodes 120, 130 and 140 of transistors. Subsequently, n-type impurity ions are implanted into a photodiode region of the active area, thereby forming a photodiode 20. Then, n-type impurity ions are implanted into the active area excluding the photodiode region, to form source and drain regions 4 for each of the transistors.
To form the source and drain regions 4, N-type impurity ions are implanted at a low density using the gate electrodes 120, 130 and 140 as a mask, thereby forming an LDD (Lightly Doped Drain) region. After forming insulating sidewalls 5 at sides of the respective gate electrodes 120, 130 and 140, n-type impurity ions may be implanted at a high density, thereby forming the source and drain regions 4 for the transistors.
As shown in FIG. 5B, a PMD (Pre-Metal Dielectric) 90 made of, for example, TEOS oxide, may be formed on the surface of the semiconductor substrate 1 including the gate electrodes 120, 130 and 140 by LPCVD, whereby a first insulating interlayer 14 may be formed at a thickness of about 1000 Å.
Then, a contact hole 6 for exposing the source and drain regions 4 is formed by selectively etching the first insulating interlayer 14. Then, a metal layer is deposited and selectively etched to form a first metal line M1. The contact hole 6 may be formed by a plasma etching process.
In the same method explained in FIG. 4, respective insulating interlayers 15, 16 and 17 and metal lines M2 and M3 are formed, and a planarization layer 18 is formed on the fourth insulating interlayer 17. Thereafter, an RGB color filter layer 19, for realizing a color image, is formed on the planarization layer 18, and a micro-lens 21 is formed on the color filter layer 19.
However, the CMOS image sensor and the method for manufacturing the same according to the related art have the following disadvantages.
First, the photodiode region is positioned at a lower side of the semiconductor substrate, and the insulating layers and metal lines are formed over the photodiode region. As a result, the size of the light-receiving area for the photodiode is restricted. Also, it is impossible to form the metal line over the photodiode. Accordingly, the design of the metal line is restricted.
Due to the thickness of the metal line and the insulating interlayer, the light-receiving efficiency of the photodiode is lowered. Thus, it is necessary to form an additional micro-lens.